The present disclosure relates to a successive approximation AD converter, and more particularly to a successive approximation AD converter provided with a capacitance array type DA converter.
The successive approximation AD converter is configured to achieve multi-bit analog-to-digital conversion (AD conversion) by successively repeating comparison operation between an analog input voltage and a voltage generated by a digital-to-analog converter (hereinafter referred to as a DAC) from the highest-order bit to the lowest-order bit. The successive comparison operation includes controlling a digital input signal of the DAC based on the comparison result of the previous bit to generate a comparison target voltage for the next bit.
As the DAC, a capacitance array where capacitance values are weighted with a binary (powers of 2) ratio is often used. When such a capacitance array type DAC (hereinafter referred to as a capacitance DAC) is used, the capacitance value of a capacitance array corresponding to higher-order bits will increase as the number of bits increase, causing increase in the area and power consumption of the AD converter. To address this problem, a technique has been proposed where the capacitance array is divided into a higher-order part and a lower-order part and such parts are coupled by a coupling capacitor, thereby reducing the capacitance value of a capacitance array corresponding to higher-order bits (see Japanese Unexamined Patent Publication No. H02-155457, for example).
FIG. 7 shows a configuration of a typical 8-bit successive approximation AD converter. This successive approximation AD converter includes: a switch 1 that samples an analog input voltage; a capacitance DAC 200; a comparator 3; a latch circuit 4 that stores a comparison result; a successive approximation circuit 5 that outputs an 8-bit digital signal constituted by signals P1 to P8 based on an output signal of the latch circuit 4; and a serial-to-parallel conversion circuit 6 that converts the output signal of the latch circuit 4 to a multi-bit signal.
The capacitance DAC 200 includes: a higher-order side capacitance array (hereinafter referred to as a higher-order DAC) 201 and a lower-order side capacitance array (hereinafter referred to as a lower-order DAC) 202, where capacitance values are weighted with a binary ratio; and a coupling capacitor 203 that couples these arrays. The higher-order DAC 201 includes capacitive elements c1, c2, c3, and c4 and is configured so that a first terminal of each of the capacitive elements is connected to a common node and a second terminal thereof is independently connected to either a reference voltage VH or VL (where VH>VL) via a switch. The lower-order DAC 202 includes capacitive elements c5, c6, c7, and c8 and is configured so that a first terminal of each of the capacitive elements is connected to a common node and a second terminal thereof is independently connected to either the reference voltage VH or VL via a switch. Note that the capacitance values of the capacitive elements c1 to c8 are indicated near the corresponding capacitive elements in FIG. 7.
The operation of the successive approximation AD converter is as follows. First, the switch 1 is turned on to sample an analog input voltage. At this time, the digital signal input into the capacitance DAC 200 from the successive approximation circuit 5 is set to its initial value, which is (P1, P2, P3, P4, P5, P6, P7, P8)=(1, 0, 0, 0, 0, 0, 0, 0). The second terminal of each of the capacitive elements c1 to c8 is connected to VH when the corresponding bit of the input digital signal is 1 and to VL when it is 0. Therefore, the analog input voltage is first compared with a voltage corresponding to (VH−VL)/2, and which one of the voltages is large is decided by the comparator 3. The comparison result is stored in the latch circuit 4, whereby the value of the MSB of the output digital signal is determined, and also the digital signal output from the successive approximation circuit 5 is updated, whereby a comparison target voltage for the next bit is generated in the capacitance DAC 200.
More specifically, when the MSB is determined as 1, the signal P2 corresponding to the next bit is changed from 0 to 1 while the signal P1 corresponding to the highest-order bit is kept 1. By this change, the analog input voltage is compared with a voltage corresponding to 3 (VH−VL)/4, and which one of the voltages is large is decided by the comparator 3, to determine the value of the next bit. On the other hand, when the MSB is determined as 0, the signal P1 corresponding to the highest-order bit is changed to 1 to 0, and the signal P2 corresponding to the next bit is changed from 0 to 1. By this change, the analog input voltage is compared with a voltage corresponding to (VH−VL)/4, and which one of the voltages is large is decided by the comparator 3, to determine the value of the next bit.
The operation described above is repeated successively until the LSB of the output digital signal is determined. Finally, after the comparison decision results for all the bits are temporarily stored in the latch circuit 4, an 8-bit AD converted value is output from the serial-to-parallel conversion circuit 6 that is constituted by shift registers.
However, since a parasitic capacitance cp is generally present in the capacitance DAC 200, the weighting becomes different between the higher-order part and the lower-order part of the capacitance DAC 200, worsening the AD conversion precision. To address this problem, a technique is proposed where a variable capacitive element is provided in the lower-order part of the capacitance DAC and adjusted so that the charge transfer amount of the capacitive element corresponding to the lowest-order bit in the higher-order part and that of all the capacitive elements in the lower-order part are equal to each other (see Japanese Unexamined Patent Publication No. 2010-45723, for example).
Reducing the capacitance in a successive approximation AD converter having a capacitance DAC worsens mismatch precision, failing to produce capacitance values weighted with a correct binary ratio. In particular, degradation in the relative precision of a capacitance corresponding to a higher-order bit greatly affects degradation in AD conversion precision. While the mismatch precision can be improved by using a large capacitance, the increase in the capacitance of the capacitance DAC causes increase in the area and power of the entire AD converter. Also, in the technique of adjusting the higher-order part and lower-order part of the capacitance DAC described above, the voltage value at the time when the capacitive element corresponding to the lowest-order bit in the higher-order part and all the capacitive elements in the lower-order part are changed over with a switch is determined by a comparator. Therefore, no precise correction is possible when an offset is present in the comparator.
An AD converted value with good linearity and high precision depends on the precision of the capacitance values weighted with a binary ratio in the capacitance DAC. However, because of the above-described problems such as the deterioration in mismatch precision due to the capacitance reduction and the difference in weighting between the higher-order DAC and the lower-order DAC due to a parasitic capacitance in the lower-order DAC, an error occurs in the output of the capacitance DAC. As a result, the AD conversion results have nonlinear characteristics.
In view of the above, there is a need for a successive approximation AD converter with improved mismatch precision. Further, there is a need for a small-sized, low-power successive approximation AD converter capable of producing a high-precision AD converted value by correcting an error in the capacitance DAC even if an offset is present in the comparator.